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[转]65c02指令集  

2008-03-28 21:15:12|  分类: PCE资料 |  标签: |举报 |字号 订阅

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65c02指令集 
算是很古早的cpu, 
為6502加強版,算是一顆模擬接近16位元的cpu. 
 
很久以前的東西,找到順便放上來, 
接著要消失一段時間了。 
 
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|Written by Jonathan Bowen | 
| Programming Research Group | 
| Oxford University Computing Laboratory | 
| 8-11 Keble Road | 
| Oxford OX1 3QD | 
| England | 
| | 
| Tel +44-865-273840 | 
| | 
|Created November 1984 | 
|Updated April 1985 | 
|Issue 1.1 Copyright (C) J.P.Bowen 1985| 
---------------------------------------------------------------- 
---------------------------------------------------------------- 
|Mnem. |Op|NVBDIZC|A#ZBIRX@|~|Description |Notes | 
|------+--+-------+--------+-+---------------------+-----------| 
|ADC s|6D|**---**| XxX XX|4|Add with Carry |A=A+s+C %| 
|AND s|2D|*----*-| XxX XX|4|Logical AND |A=A&s %| 
|ASL d|0E|*----**| xx |6|Arith. Shift Left |d={C,d,0}{0,d,C}| 
|LSRA |4A|0----**|X |2|Logical Shift Right |A=->{0,A,C}| 
|NOP |EA|-------| X |2|No Operation | | 
|ORA s|0D|*----*-| XxX XX|4|Logical Inclusive OR |A=Avs | 
|PHA |48|-------| X |3|Push Accumulator |-[S]=A | 
|PHP |08|-------| X |3|Push status register |-[S]=P | 
|PHX |DA|-------| X |2|Push index register |-[S]=X | 
|PHY |5A|-------| X |2|Push index register |-[S]=Y | 
|PLA |68|-------| X |4|Pull Accumulator |A=[S]+ | 
|PLP |28|*******| X |4|Pull status register |P=[S]+ | 
|PLX |FA|-------| X |2|Pull index register |X=[S]+ | 
|PLY |7A|-------| X |2|Pull index register |Y=[S]+ | 
|RMBb d|07|-------| * |5|Reset Memory Bit |d=0 | 
|ROL d|2E|*----**| xx |6|Rotate Left |d={C,d}{C,d} | 
|RORA |6A|*----**|X |2|Rotate Right Acc. |A=->{C,A} | 
|RTI |40|*******| X |6|Return from Interrupt|{PC,P}=[S]+| 
|RTS |60|-------| X |6|Return from Subr. |PC={[S]+}+1| 
|SBC s|ED|*----**| XxX XX|4|Subtract with Carry |A=A-s-C %| 
|SEC |38|------1| X |2|Set Carry flag |C=1 | 
|SED |F8|---1---| X |2|Set Decimal mode |D=1 | 
|SEI |78|----1--| X |2|Set Interrupt disable|I=1 | 
|SMBb d|87|-------| * |5|Set Memory Bit |d=1 | 
|STA d|8D|-------| xX XX|4|Store Accumulator |d=A | 
|STX d|8E|-------| y* |4|Store index register |d=X | 
|STY d|8C|-------| x* |4|Store index register |d=Y | 
|STZ d|9C|-------| xx |4|Store Zero |d=0 $| 
|TAX |AA|*----*-| X |2|Transfer Accumulator |X=A | 
|TAY |A8|*----*-| X |2|Transfer Accumulator |Y=A | 
|TRB d|1C|**---*-| ** |2|Test and Reset Bits |d=~A&d | 
|TSB d|0C|**---*-| ** |2|Test and Set Bits |d=Avd | 
|TSX |BA|*----*-| X |2|Transfer Stack ptr |X=S | 
|TXA |8A|*----*-| X |2|Transfer index reg. |A=X | 
|TXS |9A|-------| X |2|Transfer index reg. |S=X | 
|TYA |98|*----*-| X |2|Transfer index reg. |A=Y | 
|------+--+-------+--------+-+---------------------------------| 
| |XX| | |X|Hexadecimal opcode/no. of cycles | 
---------------------------------------------------------------- 
---------------------------------------------------------------- 
|Mnemonic |NVBDIZC|A#ZBIRX@|Description
|---------+-------+--------+-----------------------------------| 
| P |-*01+ | |Unaff/affected/reset/set/stack set | 
| N |N | |Negative status (Bit 7) | 
| V | V | |Overflow status (Bit 6) | 
| B | B | |Break command indicator (Bit 4) | 
| D | D | |Decimal mode control (Bit 3) | 
| I | I | |Interrupt disable control (Bit 2) | 
| Z | Z | |Zero status (Bit 1) | 
| C | C| |Carry status (Bit 0) | 
|------------------+--------+----------------------------------| 
| |* |Only non-indexed mode valid | 
| |x |X and non-indexed mode valid | 
| |y |Y and non-indexed mode valid | 
| |X |All modes valid | 
|-----------------+--------+-----------------------------------| 
| | |Add XXH to opcode |+XXH| | 
| | |Subtract XXH from opcode |-XXH| | 
| | |Add X to number of cycles | |+X| 
| | |Subtract X from cycles | |-X| 
|-----------------+--------+---------------------------+----+--| 
| b | |Bit number (b=0-7) |+b0H| | 
| A |A |Accumulator | | | 
| #n | # |Immediate |-0CH|-2| 
| #n | # | ditto (opcode = XDH) | X9H| 2| 
| BIT #n | # | ditto (special case) | 89H| 2| 
| | STZ n | Z | ditto (special case) | 64H| 3| 
| n | * |Zero page (direct mode) |-08H|-1| 
| n,X | x |Zero page indexed (X) |+08H|+0| 
| n,Y | y |Zero Page indexed (Y) |+08H|+0| 
| >nn | B |Absolute |+00H|+0| 
| nn | * |Absolute (extended mode) |+00H|+0| 
| nn,X | x |Absolute indexed (X) |+10H|+0| 
| nn,Y | y |Absolute indexed (Y) |+0CH|+0| 
| LDX nn,Y | y | ditto (special case) | BEH| 4| 
| | I |Implicit | | | 
| a | R |Relative (PC=PC+1+offset) | |+2| 
| [nn,X] | x |Indexed indirect (X) |-0CH|+2| 
| [nn],Y | y |Indirect indexed (Y) |+04H|+1| 
| [nn] | @|Absolute indirect |+05H|+1| 
| JMP [nn] | @| ditto (special case) | 6CH| 5| 
|--------------------------+-----------------------------------| 
| A |Accumulator (8-bit) | 
| P |Processor status register (8-bit) | 
| PC |Program Counter (16-bit) | 
| S |Stack pointer (9-bit, MSB=1) | 
| X |Index register X (8-bit) | 
| Y |Index register Y (8-bit) | 
|--------------------------+-----------------------------------| 
| a |Relative address (-128 to +127) | 
| b |Bit number (0 to 7) | 
| d |Destination | 
| n |8-bit expression (0 to 255) | 
| nn |16-bit expression (0 to 65535) | 
| s |Source | 
| z |Zero page, relative address (n,a) | 
|--------------------------+-----------------------------------| 
| + - |Arithmetic addition/subtraction | 
| * / |Arithmetic multiplication/division | 
| & ~ |Logical AND/NOT | 
| v x |Logical inclusive/exclusive OR | 
|  |Rotate left/right | 
| [ ] |Indirect addressing | 
| [ ]+ |Post-increment indirect addressing | 
| -[ ] |Pre-decrement indirect addressing | 
| { } |Combination of operands | 
|  |Bit number | 
| $ |Special case for addressing mode | 
| % |~s=~s+1 if crossing page boundary | 
|--------------------------+-----------------------------------| 
|0000H to 00FFH |Page 0 (see zero page addressing) | 
|0100H to 01FFH |Page 1 (stack area, 01FFH = start) | 
|XX00H to XXFFH |Page n (where n=XXH) | 
|FFFAH to FFFBH |Non maskable interrupt vector(NMI) | 
|FFFCH to FFFDH |Reset (RES) vector | 
|FFFEH to FFFFH |Interrupt Request vector (IRQ) | 
|FFFEH to FFFFH |Break command vector (see BRK) | 
----------------------------------------------------------------

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